// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.10.3.144
// Netlist written on Wed Sep 14 11:46:07 2022
//
// Verilog Description of module timer
//

module timer (clk, rst_n, T, duty, intr, pwm) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(21[8:13])
    input clk;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(22[8:11])
    input rst_n;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(23[8:13])
    input [31:0]T;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    input [31:0]duty;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    output [0:0]intr;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(26[22:26])
    output pwm;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(27[9:12])
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(22[8:11])
    
    wire GND_net, VCC_net, rst_n_c, T_c_31, T_c_30, T_c_29, T_c_28, 
        T_c_27, T_c_26, T_c_25, T_c_24, T_c_23, T_c_22, T_c_21, 
        T_c_20, T_c_19, T_c_18, T_c_17, T_c_16, T_c_15, T_c_14, 
        T_c_13, T_c_12, T_c_11, T_c_10, T_c_9, T_c_8, T_c_7, T_c_6, 
        T_c_5, T_c_4, T_c_3, T_c_2, T_c_1, T_c_0, duty_c_31, duty_c_30, 
        duty_c_29, duty_c_28, duty_c_27, duty_c_26, duty_c_25, duty_c_24, 
        duty_c_23, duty_c_22, duty_c_21, duty_c_20, duty_c_19, duty_c_18, 
        duty_c_17, duty_c_16, duty_c_15, duty_c_14, duty_c_13, duty_c_12, 
        duty_c_11, duty_c_10, duty_c_9, duty_c_8, duty_c_7, duty_c_6, 
        duty_c_5, duty_c_4, duty_c_3, duty_c_2, duty_c_1, duty_c_0, 
        intr_c_0, pwm_c;
    wire [31:0]Cnt;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(30[22:25])
    
    wire n255, intr_0__N_1, pwm_N_69, n254, n165, n164, n163, 
        n162, n161, n160, n159, n158, n157, n156, n155, n154, 
        n153, n152, n151, n150, n149, n148, n147, n146, n145, 
        n144, n143, n142, n141, n140, n139, n138, n137, n136, 
        n135, n134, n253, n252, n251, n250, n249, n248, n247, 
        n246, n245, n244, n243, n242, n241, n240, n239, n238, 
        n237, n236, n235, n234, n233, n232, n231, n230, n229, 
        n228, n227, n226, n225, n224, n223, n199, n256, n257, 
        n258, n259, n260, n261, n262, n263, n264, n265, n266, 
        n267, n268, n269, n270;
    
    VHI i34 (.Z(VCC_net));
    LUT4 i31_2_lut (.A(n165), .B(intr_0__N_1), .Z(n199)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam i31_2_lut.init = 16'heeee;
    CCU2D sub_22_add_2_31 (.A0(duty_c_29), .B0(Cnt[29]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_30), .B1(Cnt[30]), .C1(GND_net), 
          .D1(GND_net), .CIN(n253), .COUT(n254));
    defparam sub_22_add_2_31.INIT0 = 16'h5999;
    defparam sub_22_add_2_31.INIT1 = 16'h5999;
    defparam sub_22_add_2_31.INJECT1_0 = "NO";
    defparam sub_22_add_2_31.INJECT1_1 = "NO";
    FD1P3AX pwm_reg_0__16 (.D(pwm_N_69), .SP(rst_n_c), .CK(clk_c), .Q(pwm_c));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(39[7] 44[5])
    defparam pwm_reg_0__16.GSR = "DISABLED";
    FD1S3AX Cnt_25__i0 (.D(n199), .CK(clk_c), .Q(Cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i0.GSR = "ENABLED";
    CCU2D sub_22_add_2_29 (.A0(duty_c_27), .B0(Cnt[27]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_28), .B1(Cnt[28]), .C1(GND_net), 
          .D1(GND_net), .CIN(n252), .COUT(n253));
    defparam sub_22_add_2_29.INIT0 = 16'h5999;
    defparam sub_22_add_2_29.INIT1 = 16'h5999;
    defparam sub_22_add_2_29.INJECT1_0 = "NO";
    defparam sub_22_add_2_29.INJECT1_1 = "NO";
    OB intr_pad_0 (.I(intr_c_0), .O(intr[0]));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(26[22:26])
    VLO i1 (.Z(GND_net));
    TSALL TSALL_INST (.TSALL(GND_net));
    FD1S3IX Cnt_25__i31 (.D(n134), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[31])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i31.GSR = "ENABLED";
    OB pwm_pad (.I(pwm_c), .O(pwm));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(27[9:12])
    GSR GSR_INST (.GSR(rst_n_c));
    CCU2D Cnt_25_add_4_33 (.A0(Cnt[31]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n270), 
          .S0(n134));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_33.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_33.INIT1 = 16'h0000;
    defparam Cnt_25_add_4_33.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_33.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_31 (.A0(Cnt[29]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[30]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n269), 
          .COUT(n270), .S0(n136), .S1(n135));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_31.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_31.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_31.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_31.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_29 (.A0(Cnt[27]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[28]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n268), 
          .COUT(n269), .S0(n138), .S1(n137));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_29.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_29.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_29.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_29.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_27 (.A0(Cnt[25]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[26]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n267), 
          .COUT(n268), .S0(n140), .S1(n139));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_27.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_27.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_27.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_27.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_25 (.A0(Cnt[23]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[24]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n266), 
          .COUT(n267), .S0(n142), .S1(n141));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_25.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_25.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_25.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_25.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_23 (.A0(Cnt[21]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[22]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n265), 
          .COUT(n266), .S0(n144), .S1(n143));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_23.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_23.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_23.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_23.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_21 (.A0(Cnt[19]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[20]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n264), 
          .COUT(n265), .S0(n146), .S1(n145));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_21.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_21.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_21.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_21.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_19 (.A0(Cnt[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[18]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n263), 
          .COUT(n264), .S0(n148), .S1(n147));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_19.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_19.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_19.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_19.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_17 (.A0(Cnt[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n262), 
          .COUT(n263), .S0(n150), .S1(n149));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_17.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_17.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_17.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_17.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_15 (.A0(Cnt[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n261), 
          .COUT(n262), .S0(n152), .S1(n151));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_15.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_15.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_15.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_15.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_13 (.A0(Cnt[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n260), 
          .COUT(n261), .S0(n154), .S1(n153));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_13.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_13.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_13.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_13.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_11 (.A0(Cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n259), 
          .COUT(n260), .S0(n156), .S1(n155));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_11.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_11.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_11.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_11.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_9 (.A0(Cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n258), 
          .COUT(n259), .S0(n158), .S1(n157));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_9.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_9.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_9.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_9.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_7 (.A0(Cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n257), 
          .COUT(n258), .S0(n160), .S1(n159));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_7.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_7.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_7.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_7.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_5 (.A0(Cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n256), 
          .COUT(n257), .S0(n162), .S1(n161));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_5.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_5.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_5.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_5.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_3 (.A0(Cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n255), 
          .COUT(n256), .S0(n164), .S1(n163));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_3.INIT0 = 16'hfaaa;
    defparam Cnt_25_add_4_3.INIT1 = 16'hfaaa;
    defparam Cnt_25_add_4_3.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_3.INJECT1_1 = "NO";
    CCU2D Cnt_25_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n255), 
          .S1(n165));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25_add_4_1.INIT0 = 16'hF000;
    defparam Cnt_25_add_4_1.INIT1 = 16'h0555;
    defparam Cnt_25_add_4_1.INJECT1_0 = "NO";
    defparam Cnt_25_add_4_1.INJECT1_1 = "NO";
    FD1S3AX intr_0__15 (.D(intr_0__N_1), .CK(clk_c), .Q(intr_c_0));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(39[7] 44[5])
    defparam intr_0__15.GSR = "ENABLED";
    FD1S3IX Cnt_25__i30 (.D(n135), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[30])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i30.GSR = "ENABLED";
    FD1S3IX Cnt_25__i29 (.D(n136), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[29])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i29.GSR = "ENABLED";
    FD1S3IX Cnt_25__i28 (.D(n137), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[28])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i28.GSR = "ENABLED";
    FD1S3IX Cnt_25__i27 (.D(n138), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[27])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i27.GSR = "ENABLED";
    FD1S3IX Cnt_25__i26 (.D(n139), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[26])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i26.GSR = "ENABLED";
    FD1S3IX Cnt_25__i25 (.D(n140), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[25])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i25.GSR = "ENABLED";
    FD1S3IX Cnt_25__i24 (.D(n141), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[24])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i24.GSR = "ENABLED";
    FD1S3IX Cnt_25__i23 (.D(n142), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i23.GSR = "ENABLED";
    FD1S3IX Cnt_25__i22 (.D(n143), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i22.GSR = "ENABLED";
    FD1S3IX Cnt_25__i21 (.D(n144), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i21.GSR = "ENABLED";
    FD1S3IX Cnt_25__i20 (.D(n145), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i20.GSR = "ENABLED";
    FD1S3IX Cnt_25__i19 (.D(n146), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i19.GSR = "ENABLED";
    FD1S3IX Cnt_25__i18 (.D(n147), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i18.GSR = "ENABLED";
    FD1S3IX Cnt_25__i17 (.D(n148), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i17.GSR = "ENABLED";
    FD1S3IX Cnt_25__i16 (.D(n149), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i16.GSR = "ENABLED";
    FD1S3IX Cnt_25__i15 (.D(n150), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i15.GSR = "ENABLED";
    FD1S3IX Cnt_25__i14 (.D(n151), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i14.GSR = "ENABLED";
    FD1S3IX Cnt_25__i13 (.D(n152), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i13.GSR = "ENABLED";
    FD1S3IX Cnt_25__i12 (.D(n153), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i12.GSR = "ENABLED";
    FD1S3IX Cnt_25__i11 (.D(n154), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i11.GSR = "ENABLED";
    FD1S3IX Cnt_25__i10 (.D(n155), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i10.GSR = "ENABLED";
    FD1S3IX Cnt_25__i9 (.D(n156), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i9.GSR = "ENABLED";
    FD1S3IX Cnt_25__i8 (.D(n157), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i8.GSR = "ENABLED";
    FD1S3IX Cnt_25__i7 (.D(n158), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i7.GSR = "ENABLED";
    FD1S3IX Cnt_25__i6 (.D(n159), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i6.GSR = "ENABLED";
    FD1S3IX Cnt_25__i5 (.D(n160), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i5.GSR = "ENABLED";
    FD1S3IX Cnt_25__i4 (.D(n161), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i4.GSR = "ENABLED";
    FD1S3IX Cnt_25__i3 (.D(n162), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i3.GSR = "ENABLED";
    FD1S3IX Cnt_25__i2 (.D(n163), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i2.GSR = "ENABLED";
    FD1S3IX Cnt_25__i1 (.D(n164), .CK(clk_c), .CD(intr_0__N_1), .Q(Cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/timer.v(41[21:31])
    defparam Cnt_25__i1.GSR = "ENABLED";
    CCU2D sub_22_add_2_33 (.A0(duty_c_31), .B0(Cnt[31]), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n254), .S1(pwm_N_69));
    defparam sub_22_add_2_33.INIT0 = 16'h5999;
    defparam sub_22_add_2_33.INIT1 = 16'h0000;
    defparam sub_22_add_2_33.INJECT1_0 = "NO";
    defparam sub_22_add_2_33.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_27 (.A0(duty_c_25), .B0(Cnt[25]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_26), .B1(Cnt[26]), .C1(GND_net), 
          .D1(GND_net), .CIN(n251), .COUT(n252));
    defparam sub_22_add_2_27.INIT0 = 16'h5999;
    defparam sub_22_add_2_27.INIT1 = 16'h5999;
    defparam sub_22_add_2_27.INJECT1_0 = "NO";
    defparam sub_22_add_2_27.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_25 (.A0(duty_c_23), .B0(Cnt[23]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_24), .B1(Cnt[24]), .C1(GND_net), 
          .D1(GND_net), .CIN(n250), .COUT(n251));
    defparam sub_22_add_2_25.INIT0 = 16'h5999;
    defparam sub_22_add_2_25.INIT1 = 16'h5999;
    defparam sub_22_add_2_25.INJECT1_0 = "NO";
    defparam sub_22_add_2_25.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_23 (.A0(duty_c_21), .B0(Cnt[21]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_22), .B1(Cnt[22]), .C1(GND_net), 
          .D1(GND_net), .CIN(n249), .COUT(n250));
    defparam sub_22_add_2_23.INIT0 = 16'h5999;
    defparam sub_22_add_2_23.INIT1 = 16'h5999;
    defparam sub_22_add_2_23.INJECT1_0 = "NO";
    defparam sub_22_add_2_23.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_21 (.A0(duty_c_19), .B0(Cnt[19]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_20), .B1(Cnt[20]), .C1(GND_net), 
          .D1(GND_net), .CIN(n248), .COUT(n249));
    defparam sub_22_add_2_21.INIT0 = 16'h5999;
    defparam sub_22_add_2_21.INIT1 = 16'h5999;
    defparam sub_22_add_2_21.INJECT1_0 = "NO";
    defparam sub_22_add_2_21.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_19 (.A0(duty_c_17), .B0(Cnt[17]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_18), .B1(Cnt[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n247), .COUT(n248));
    defparam sub_22_add_2_19.INIT0 = 16'h5999;
    defparam sub_22_add_2_19.INIT1 = 16'h5999;
    defparam sub_22_add_2_19.INJECT1_0 = "NO";
    defparam sub_22_add_2_19.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_17 (.A0(duty_c_15), .B0(Cnt[15]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_16), .B1(Cnt[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n246), .COUT(n247));
    defparam sub_22_add_2_17.INIT0 = 16'h5999;
    defparam sub_22_add_2_17.INIT1 = 16'h5999;
    defparam sub_22_add_2_17.INJECT1_0 = "NO";
    defparam sub_22_add_2_17.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_15 (.A0(duty_c_13), .B0(Cnt[13]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_14), .B1(Cnt[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n245), .COUT(n246));
    defparam sub_22_add_2_15.INIT0 = 16'h5999;
    defparam sub_22_add_2_15.INIT1 = 16'h5999;
    defparam sub_22_add_2_15.INJECT1_0 = "NO";
    defparam sub_22_add_2_15.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_13 (.A0(duty_c_11), .B0(Cnt[11]), .C0(GND_net), 
          .D0(GND_net), .A1(duty_c_12), .B1(Cnt[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n244), .COUT(n245));
    defparam sub_22_add_2_13.INIT0 = 16'h5999;
    defparam sub_22_add_2_13.INIT1 = 16'h5999;
    defparam sub_22_add_2_13.INJECT1_0 = "NO";
    defparam sub_22_add_2_13.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_11 (.A0(duty_c_9), .B0(Cnt[9]), .C0(GND_net), .D0(GND_net), 
          .A1(duty_c_10), .B1(Cnt[10]), .C1(GND_net), .D1(GND_net), 
          .CIN(n243), .COUT(n244));
    defparam sub_22_add_2_11.INIT0 = 16'h5999;
    defparam sub_22_add_2_11.INIT1 = 16'h5999;
    defparam sub_22_add_2_11.INJECT1_0 = "NO";
    defparam sub_22_add_2_11.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_9 (.A0(duty_c_7), .B0(Cnt[7]), .C0(GND_net), .D0(GND_net), 
          .A1(duty_c_8), .B1(Cnt[8]), .C1(GND_net), .D1(GND_net), .CIN(n242), 
          .COUT(n243));
    defparam sub_22_add_2_9.INIT0 = 16'h5999;
    defparam sub_22_add_2_9.INIT1 = 16'h5999;
    defparam sub_22_add_2_9.INJECT1_0 = "NO";
    defparam sub_22_add_2_9.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_7 (.A0(duty_c_5), .B0(Cnt[5]), .C0(GND_net), .D0(GND_net), 
          .A1(duty_c_6), .B1(Cnt[6]), .C1(GND_net), .D1(GND_net), .CIN(n241), 
          .COUT(n242));
    defparam sub_22_add_2_7.INIT0 = 16'h5999;
    defparam sub_22_add_2_7.INIT1 = 16'h5999;
    defparam sub_22_add_2_7.INJECT1_0 = "NO";
    defparam sub_22_add_2_7.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_5 (.A0(duty_c_3), .B0(Cnt[3]), .C0(GND_net), .D0(GND_net), 
          .A1(duty_c_4), .B1(Cnt[4]), .C1(GND_net), .D1(GND_net), .CIN(n240), 
          .COUT(n241));
    defparam sub_22_add_2_5.INIT0 = 16'h5999;
    defparam sub_22_add_2_5.INIT1 = 16'h5999;
    defparam sub_22_add_2_5.INJECT1_0 = "NO";
    defparam sub_22_add_2_5.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_3 (.A0(duty_c_1), .B0(Cnt[1]), .C0(GND_net), .D0(GND_net), 
          .A1(duty_c_2), .B1(Cnt[2]), .C1(GND_net), .D1(GND_net), .CIN(n239), 
          .COUT(n240));
    defparam sub_22_add_2_3.INIT0 = 16'h5999;
    defparam sub_22_add_2_3.INIT1 = 16'h5999;
    defparam sub_22_add_2_3.INJECT1_0 = "NO";
    defparam sub_22_add_2_3.INJECT1_1 = "NO";
    CCU2D sub_22_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(duty_c_0), .B1(Cnt[0]), .C1(GND_net), .D1(GND_net), .COUT(n239));
    defparam sub_22_add_2_1.INIT0 = 16'h0000;
    defparam sub_22_add_2_1.INIT1 = 16'h5999;
    defparam sub_22_add_2_1.INJECT1_0 = "NO";
    defparam sub_22_add_2_1.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_33 (.A0(Cnt[31]), .B0(T_c_31), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n238), 
          .S1(intr_0__N_1));
    defparam sub_21_add_2_33.INIT0 = 16'h5999;
    defparam sub_21_add_2_33.INIT1 = 16'h0000;
    defparam sub_21_add_2_33.INJECT1_0 = "NO";
    defparam sub_21_add_2_33.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_31 (.A0(Cnt[29]), .B0(T_c_29), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[30]), .B1(T_c_30), .C1(GND_net), .D1(GND_net), .CIN(n237), 
          .COUT(n238));
    defparam sub_21_add_2_31.INIT0 = 16'h5999;
    defparam sub_21_add_2_31.INIT1 = 16'h5999;
    defparam sub_21_add_2_31.INJECT1_0 = "NO";
    defparam sub_21_add_2_31.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_29 (.A0(Cnt[27]), .B0(T_c_27), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[28]), .B1(T_c_28), .C1(GND_net), .D1(GND_net), .CIN(n236), 
          .COUT(n237));
    defparam sub_21_add_2_29.INIT0 = 16'h5999;
    defparam sub_21_add_2_29.INIT1 = 16'h5999;
    defparam sub_21_add_2_29.INJECT1_0 = "NO";
    defparam sub_21_add_2_29.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_27 (.A0(Cnt[25]), .B0(T_c_25), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[26]), .B1(T_c_26), .C1(GND_net), .D1(GND_net), .CIN(n235), 
          .COUT(n236));
    defparam sub_21_add_2_27.INIT0 = 16'h5999;
    defparam sub_21_add_2_27.INIT1 = 16'h5999;
    defparam sub_21_add_2_27.INJECT1_0 = "NO";
    defparam sub_21_add_2_27.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_25 (.A0(Cnt[23]), .B0(T_c_23), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[24]), .B1(T_c_24), .C1(GND_net), .D1(GND_net), .CIN(n234), 
          .COUT(n235));
    defparam sub_21_add_2_25.INIT0 = 16'h5999;
    defparam sub_21_add_2_25.INIT1 = 16'h5999;
    defparam sub_21_add_2_25.INJECT1_0 = "NO";
    defparam sub_21_add_2_25.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_23 (.A0(Cnt[21]), .B0(T_c_21), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[22]), .B1(T_c_22), .C1(GND_net), .D1(GND_net), .CIN(n233), 
          .COUT(n234));
    defparam sub_21_add_2_23.INIT0 = 16'h5999;
    defparam sub_21_add_2_23.INIT1 = 16'h5999;
    defparam sub_21_add_2_23.INJECT1_0 = "NO";
    defparam sub_21_add_2_23.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_21 (.A0(Cnt[19]), .B0(T_c_19), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[20]), .B1(T_c_20), .C1(GND_net), .D1(GND_net), .CIN(n232), 
          .COUT(n233));
    defparam sub_21_add_2_21.INIT0 = 16'h5999;
    defparam sub_21_add_2_21.INIT1 = 16'h5999;
    defparam sub_21_add_2_21.INJECT1_0 = "NO";
    defparam sub_21_add_2_21.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_19 (.A0(Cnt[17]), .B0(T_c_17), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[18]), .B1(T_c_18), .C1(GND_net), .D1(GND_net), .CIN(n231), 
          .COUT(n232));
    defparam sub_21_add_2_19.INIT0 = 16'h5999;
    defparam sub_21_add_2_19.INIT1 = 16'h5999;
    defparam sub_21_add_2_19.INJECT1_0 = "NO";
    defparam sub_21_add_2_19.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_17 (.A0(Cnt[15]), .B0(T_c_15), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[16]), .B1(T_c_16), .C1(GND_net), .D1(GND_net), .CIN(n230), 
          .COUT(n231));
    defparam sub_21_add_2_17.INIT0 = 16'h5999;
    defparam sub_21_add_2_17.INIT1 = 16'h5999;
    defparam sub_21_add_2_17.INJECT1_0 = "NO";
    defparam sub_21_add_2_17.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_15 (.A0(Cnt[13]), .B0(T_c_13), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[14]), .B1(T_c_14), .C1(GND_net), .D1(GND_net), .CIN(n229), 
          .COUT(n230));
    defparam sub_21_add_2_15.INIT0 = 16'h5999;
    defparam sub_21_add_2_15.INIT1 = 16'h5999;
    defparam sub_21_add_2_15.INJECT1_0 = "NO";
    defparam sub_21_add_2_15.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_13 (.A0(Cnt[11]), .B0(T_c_11), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[12]), .B1(T_c_12), .C1(GND_net), .D1(GND_net), .CIN(n228), 
          .COUT(n229));
    defparam sub_21_add_2_13.INIT0 = 16'h5999;
    defparam sub_21_add_2_13.INIT1 = 16'h5999;
    defparam sub_21_add_2_13.INJECT1_0 = "NO";
    defparam sub_21_add_2_13.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_11 (.A0(Cnt[9]), .B0(T_c_9), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[10]), .B1(T_c_10), .C1(GND_net), .D1(GND_net), .CIN(n227), 
          .COUT(n228));
    defparam sub_21_add_2_11.INIT0 = 16'h5999;
    defparam sub_21_add_2_11.INIT1 = 16'h5999;
    defparam sub_21_add_2_11.INJECT1_0 = "NO";
    defparam sub_21_add_2_11.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_9 (.A0(Cnt[7]), .B0(T_c_7), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[8]), .B1(T_c_8), .C1(GND_net), .D1(GND_net), .CIN(n226), 
          .COUT(n227));
    defparam sub_21_add_2_9.INIT0 = 16'h5999;
    defparam sub_21_add_2_9.INIT1 = 16'h5999;
    defparam sub_21_add_2_9.INJECT1_0 = "NO";
    defparam sub_21_add_2_9.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_7 (.A0(Cnt[5]), .B0(T_c_5), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[6]), .B1(T_c_6), .C1(GND_net), .D1(GND_net), .CIN(n225), 
          .COUT(n226));
    defparam sub_21_add_2_7.INIT0 = 16'h5999;
    defparam sub_21_add_2_7.INIT1 = 16'h5999;
    defparam sub_21_add_2_7.INJECT1_0 = "NO";
    defparam sub_21_add_2_7.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_5 (.A0(Cnt[3]), .B0(T_c_3), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[4]), .B1(T_c_4), .C1(GND_net), .D1(GND_net), .CIN(n224), 
          .COUT(n225));
    defparam sub_21_add_2_5.INIT0 = 16'h5999;
    defparam sub_21_add_2_5.INIT1 = 16'h5999;
    defparam sub_21_add_2_5.INJECT1_0 = "NO";
    defparam sub_21_add_2_5.INJECT1_1 = "NO";
    CCU2D sub_21_add_2_3 (.A0(Cnt[1]), .B0(T_c_1), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[2]), .B1(T_c_2), .C1(GND_net), .D1(GND_net), .CIN(n223), 
          .COUT(n224));
    defparam sub_21_add_2_3.INIT0 = 16'h5999;
    defparam sub_21_add_2_3.INIT1 = 16'h5999;
    defparam sub_21_add_2_3.INJECT1_0 = "NO";
    defparam sub_21_add_2_3.INJECT1_1 = "NO";
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    CCU2D sub_21_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(Cnt[0]), .B1(T_c_0), .C1(GND_net), .D1(GND_net), .COUT(n223));
    defparam sub_21_add_2_1.INIT0 = 16'h0000;
    defparam sub_21_add_2_1.INIT1 = 16'h5999;
    defparam sub_21_add_2_1.INJECT1_0 = "NO";
    defparam sub_21_add_2_1.INJECT1_1 = "NO";
    IB clk_pad (.I(clk), .O(clk_c));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(22[8:11])
    IB rst_n_pad (.I(rst_n), .O(rst_n_c));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(23[8:13])
    IB T_pad_31 (.I(T[31]), .O(T_c_31));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_30 (.I(T[30]), .O(T_c_30));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_29 (.I(T[29]), .O(T_c_29));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_28 (.I(T[28]), .O(T_c_28));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_27 (.I(T[27]), .O(T_c_27));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_26 (.I(T[26]), .O(T_c_26));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_25 (.I(T[25]), .O(T_c_25));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_24 (.I(T[24]), .O(T_c_24));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_23 (.I(T[23]), .O(T_c_23));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_22 (.I(T[22]), .O(T_c_22));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_21 (.I(T[21]), .O(T_c_21));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_20 (.I(T[20]), .O(T_c_20));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_19 (.I(T[19]), .O(T_c_19));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_18 (.I(T[18]), .O(T_c_18));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_17 (.I(T[17]), .O(T_c_17));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_16 (.I(T[16]), .O(T_c_16));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_15 (.I(T[15]), .O(T_c_15));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_14 (.I(T[14]), .O(T_c_14));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_13 (.I(T[13]), .O(T_c_13));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_12 (.I(T[12]), .O(T_c_12));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_11 (.I(T[11]), .O(T_c_11));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_10 (.I(T[10]), .O(T_c_10));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_9 (.I(T[9]), .O(T_c_9));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_8 (.I(T[8]), .O(T_c_8));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_7 (.I(T[7]), .O(T_c_7));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_6 (.I(T[6]), .O(T_c_6));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_5 (.I(T[5]), .O(T_c_5));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_4 (.I(T[4]), .O(T_c_4));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_3 (.I(T[3]), .O(T_c_3));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_2 (.I(T[2]), .O(T_c_2));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_1 (.I(T[1]), .O(T_c_1));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB T_pad_0 (.I(T[0]), .O(T_c_0));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(24[27:28])
    IB duty_pad_31 (.I(duty[31]), .O(duty_c_31));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_30 (.I(duty[30]), .O(duty_c_30));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_29 (.I(duty[29]), .O(duty_c_29));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_28 (.I(duty[28]), .O(duty_c_28));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_27 (.I(duty[27]), .O(duty_c_27));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_26 (.I(duty[26]), .O(duty_c_26));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_25 (.I(duty[25]), .O(duty_c_25));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_24 (.I(duty[24]), .O(duty_c_24));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_23 (.I(duty[23]), .O(duty_c_23));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_22 (.I(duty[22]), .O(duty_c_22));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_21 (.I(duty[21]), .O(duty_c_21));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_20 (.I(duty[20]), .O(duty_c_20));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_19 (.I(duty[19]), .O(duty_c_19));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_18 (.I(duty[18]), .O(duty_c_18));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_17 (.I(duty[17]), .O(duty_c_17));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_16 (.I(duty[16]), .O(duty_c_16));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_15 (.I(duty[15]), .O(duty_c_15));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_14 (.I(duty[14]), .O(duty_c_14));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_13 (.I(duty[13]), .O(duty_c_13));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_12 (.I(duty[12]), .O(duty_c_12));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_11 (.I(duty[11]), .O(duty_c_11));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_10 (.I(duty[10]), .O(duty_c_10));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_9 (.I(duty[9]), .O(duty_c_9));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_8 (.I(duty[8]), .O(duty_c_8));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_7 (.I(duty[7]), .O(duty_c_7));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_6 (.I(duty[6]), .O(duty_c_6));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_5 (.I(duty[5]), .O(duty_c_5));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_4 (.I(duty[4]), .O(duty_c_4));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_3 (.I(duty[3]), .O(duty_c_3));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_2 (.I(duty[2]), .O(duty_c_2));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_1 (.I(duty[1]), .O(duty_c_1));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    IB duty_pad_0 (.I(duty[0]), .O(duty_c_0));   // f:/home/mini-step-fpga/prj/h_brige/timer.v(25[30:34])
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

